As semiconductor devices have come to be more integrated and to have higher capacity, an MIM capacitor has been more frequently used in semiconductor devices. Accordingly, a method for reducing a manufacturing cost of an MIM capacitor is being investigated by eliminating both a mask and an insulating layer used as a dielectric layer that are involved in the fabrication of such an MIM capacitor.
A capacitor used for analog semiconductor devices is usually formed to have an insulating layer between polysilicons. However, a capacitor having an insulating layer between metals, such as an MIM capacitor, has recently been used for high-voltage products or System on Chip (SoC) products.
However, as design rules of a semiconductor device have been reduced, a void frequently occurs in the manufacturing process of ordinary CMOS semiconductor devices, which becomes one of deposition characteristics of an oxide layer used as the insulating layer. Such a void widely occurs in modern manufacturing processes of semiconductor devices involving, for example, a nano process or an SoC process, and a method for overcoming such a void is being investigated.
FIG. 1 and FIG. 2 are schematic diagrams illustrating an occurrence of a void created when forming an insulating layer of a conventional semiconductor device.
Referring to FIG. 1, because the size of a conventional semiconductor device such as unit transistor has become smaller, a field oxide layer 15 is firstly formed in order to insulate between active regions within a well 11 of a semiconductor substrate 10. A gate 20 of a transistor, including a polysilicon layer 23 and a silicide layer 25, is formed on a gate oxide layer 21. A spacer 27 is introduced at the sidewall of the gate 20, and a source/drain region 24 is formed by an impurity implant process in order to form other terminals of a transistor.
When a transistor is formed in such a way, a process for depositing an insulating layer 30 is performed in order to connect terminals (a CMOS device has four terminals) of a transistor to outside the transistor. Such an insulating layer 30 is usually introduced as a multi-layer structure. For example, the insulating layer 30 is formed by deposition of first, second, and third insulating layers 31, 33, and 35 having slightly different characteristics. In addition, such an insulating layer 30 is formed with an oxide layer base.
Due to deposition of the insulating layer 30, a void 37, which is an empty space in the insulating layer 30, may be created in the region where the height difference is great, because the insulating layer 30 is deposited more at an area having a large height difference than at an area having a small height difference.
Such an empty space is more frequently created in manufacturing a smaller transistor. Such a void 37 existing in the insulating layer 30 may result in a short-circuit. If a contact 41 is formed in the area having such a void 37 in order to connect a metal line 45 to a junction, such as drain region 24, the contact 41 may be connected to an adjacent contact through the void 37. In this case, as shown in FIG. 2, an electric current between adjacent transistors may consequently be applied through a conductive residual layer 47 filling in the void 37.
If such a connection problem of a contact 41 does not occur, such a void 37 and residual layer 47 may not cause severe problems of a semiconductor device itself. However, a parasitic capacitor in terms of a final product can be caused by such a void 37 and residual layer 47, and it may result in a time-delay or an alteration of the characteristics of memory data because unexpected particles, such as electrons or holes, may be contained in such a void 37 or/and residual layer 47. Therefore, it may severely deteriorate the reliability of a final product in the long run.
Therefore, a solution for overcoming such a void is being investigated in the current level of semiconductor technology.